流水灯testbench激励
module ledwater(input clk,
input rst_n,
input x,
outputreg Y
);
reg state;
reg cnt;
reg clk_div;
parameter
S0=0,
S1=1,
S2=2,
S3=3,
S4=4,
S5=5,
S6=6,
S7=7;
//******************分频模块************************//
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt<=0;
clk_div<=0;
end
else if(cnt==32'd5_000_000)
begin
clk_div<=~clk_div;
cnt<=0;
end
else
cnt<=cnt+1;
end
always@(posedge clk_div or negedge rst_n)
begin
if(!rst_n)
begin
Y<=8'b0000_0000;
state<=S0;
end
else
case(state)
S0:
begin
Y<=8'b0000_0001;
if(x==1)
state<=S0;
else
state<=S1;
end
S1:
begin
Y<=8'b0000_0010;
if(x==1)
state<=S1;
else
state<=S2;
end
S2:
begin
Y<=8'b0000_0100;
if(x==1)
state<=S2;
else
state<=S3;
end
S3:
begin
Y<=8'b0000_1000;
if(x==1)
state<=S3;
else
state<=S4;
end
S4:
begin
Y<=8'b0001_0000;
if(x==1)
state<=S4;
else
state<=S5;
end
S5:
begin
Y<=8'b0010_0000;
if(x==1)
state<=S5;
else
state<=S6;
end
S6:
begin
Y<=8'b0100_0000;
if(x==1)
state<=S6;
else
state<=S7;
end
S7:
begin
Y<=8'b1000_0000;
if(x==1)
state<=S7;
else
state<=S0;
end
default: begin Y<=8'b0000_0000;state<=S0; end
endcase
end
endmodule
这是Verilog代码，testbench的激励怎么写？
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